The present invention relates to a power protection circuitry for a semiconductor integrated circuit, which protects components of an integrated circuit from abnormal, high frequency voltage resulting from static electricity and so on applied to the power terminals of the integrated circuit. The present invention particularly relates to the power protection circuitry which protects an integrated circuit comprising MOS (Metal Oxide Semiconductor) transistors.
Conventionally, in order to protect components of a semiconductor integrated circuit from abnormal, high frequency voltage resulting from static electricity, a capacitor is inserted between a supply voltage line (Vcc) and a reference voltage line (a ground line, Vss) to absorb high frequency voltage applied to the supply voltage line from an outside source, such as from a human body.
However, the capacitor is usually connected to the supply voltage line (Vcc) and the reference voltage line (the ground line, Vss) with wiring made of aluminum, which generates inductance and resistance of the electrodes of the capacitor. Therefore, the method of using a capacitor is not sufficient for absorbing high frequency voltage completely. Even an application of a relatively low electrostatic voltage may damage PN junctions of the integrated circuit.
The conventional methods other than the one described above include a method which inserts a diode consisting of a MOS transistor with a high threshold voltage between a supply voltage line (Vcc) and a reference voltage line (the ground line, Vss). Another conventional method uses the LOGOS (local oxidization of silicon) or the selective oxidization method which isolates components with a field oxide film to form a parasitic transistor to protect components of an integrated circuit (Japanese Patent Laid-Open No. 68575/1992). Another conventional method is to insert a series circuit of a resistor and an n-channel MIS FET (Metal Insulator Semiconductor Field Effect Transistor) between a supply voltage line (Vcc) and a reference voltage line (Vss) (Japanese Patent Laid-Open No. 45850/1988).
Each of the conventional methods stated above has the following problems. In the case of the method of using a diode consisting of aMOS transistor with a high threshold voltage, an additional step of inserting a diode is required especially when the field isolation method of MOS structure is used to isolate components in an integrated circuit. The problem is that the number of steps in the manufacturing process is increased.
The method of forming a parasitic transistor by using the LOGOS isolation (Japanese Patent Laid-Open No. 68575/1992) is only effective so long as the threshold voltage of a parasitic transistor is 15V or above. It is impossible to use the method when the threshold voltage of the transistor is 2 to 10V. The method is effective so long as components of the integrated circuit are isolated using the field isolation of MOS structure. The method is, however, not applicable to those integrated circuits using other methods such as a PN junction isolation method.
In the case of the method using a series circuit of a resistor and an n-channel MIS FET (Japanese Patent Laid-Open No. 45850/1988), not only when abnormal, high frequency voltage is applied, but also during normal operation, a steady current is fed to a protective circuit, which increases power consumption during normal operation.